In data processing technologies, it is often the case that a system will read in a series of blocks of primary data, were each block is scanned in over a known interval. In such cases, the system will often then subsequently read and/or write some secondary data in response. Because such a system expects a new block of primary data at the beginning of each new interval, the system must read/write the secondary data in that same time interval, or else data buffers residing within the system will rapidly fill up and data will be lost. It is also often the case that the periodic interval may consist of an active duration, in which incoming data is received, and an inactive duration, where no data is received. The ratio of active to inactive durations is unknown, and therefore the instantaneous input data frequency relative to the interval is also unknown (but assumed to be fixed). The only known variable is the amount of data received per interval, N. The input timing of such a system is shown in timing diagram 100 of FIG. 1. An example of such a system is a video data interface in which the blanking interval is fixed, but may assume a wide range of values (from zero to 0.5TI, for example). Any dead time corresponds to an excessively high data frequency with respect to the allotted time for the transmission, i.e. the interval TI, and any secondary frequency derived from this primary frequency is also excessive and inefficient.
FIG. 2 illustrates a system 200 with a primary (input) data interface 210 and derived (secondary or output) data interface 220, where the primary interface 210 operates at frequency FP of primary clock 250, has word width P, and an average data rate of FPI words per interval, TI (FPI=N*FI). The secondary interface 220 operates at frequency FS of secondary clock 260, has word width Q, and an average data rate of FSI words per interval, TI (FSI=M*FI). Note that, in general, the secondary interface 220 may be read, write, or read/write. Data throughput or frequency on the secondary interface 220 is total throughput of any combination of read or write data on the secondary interface 220.
In FIG. 2, the primary data is buffered by data buffer 230 and accessed at some later time. The secondary data rate may, generally, be transformed by the data gain stage 240. The data gain stage 240 is intended to represent any type of operation or transformation of the primary data that increases or reduces the effective data throughput of the secondary interface 220 by some fixed multiplier, GD. Examples of such an operation include, but are not limited to, frame store (where a word read and word write must be performed for every word on the primary interface), data expansion, or reduction, through some mathematical transformation or table look-up, the a addition of overhead data words for packetizing, data compression, data packing, etc. Note that the data rate gain stage 240 may be schematically placed on either port (or both) of the data buffer without loss of generality.
For the general system of FIG. 2, if the objective is for the secondary data throughput to be greater than or equal to the primary data throughput, then the data throughput requirement on the secondary interface is given by the inequalityFSIQ≧FPIPGD  (1)
For many systems, the primary and secondary interfaces use the same clock. This arrangement is illustrated by system 300 of FIG. 3. In this simplified case, FP and FS are identical and the only degree of freedom for compensating for the data rate gain is by adjusting the width of the secondary bus. In this case the only way to accommodate a higher secondary throughput is to increase the secondary bus width Q. Consequently, the inefficiency of the clock frequency of the primary interface 210 is translated directly to the secondary interface 220. This is a result of the fact that the dead time is not known a priori and may be nearly zero, so the secondary interface 220 must be designed to take this limiting condition into account. However, if the actual dead time is greater than this minimum, as is often the case, then the inefficiency of the primary interface is translated to the secondary interface.
FIG. 4 illustrates a system 400 that implements dual edge clocking. The only change from system 300 to system 400 is that in system 400 the secondary data is dual-edge clocked, modeled as a ×2 gain 470 on the secondary clock 460. This allows the secondary bus width Q to be reduced by a factor of 2 relative to system 300, but Q remains the sole method of increasing secondary bus throughput. This system also suffers from same inefficiency as system 300.
FIG. 5 illustrates a system 500 that implements a general multiplication function on the secondary clock. In system 500, the general multiplication function is performed by a “clock-locked” phase-locked loop (PLL) 570. The PLL 570 generates a secondary clock 560 frequency that proportional to the primary clock 250 and the modeling can generally include a 2× gain for secondary interface dual-edge clocking. This configuration has the advantage that an additional degree of freedom achieving the secondary throughput requirement, which can now be achieved using a combination of secondary interface width Q and the secondary clock frequency FS. However, because of the zero-dead-time constraint, the inefficiency of the primary interface 210 is translated to the secondary interface 220 in this case, as in both system 300 and system 400.
FIG. 6 illustrates a timing diagram 600 for a timing system in which the secondary clock frequency FS is proportional to the primary clock frequency FP. As stated above, because the secondary clock frequency FS is proportional to the primary clock frequency FP, the secondary interface 220 will fall prey to the zero-dead-time constraint. Thus, the blanking time 612 of the primary data transmission 621 appears as blanking time 622 in the secondary data transmission 621. The excessive frequency seen in the secondary interface 220 translates into excessive power consumption and excessive heat generation. Furthermore, the excessively high secondary frequency may also require the use of unnecessarily fast external circuitry. For example, consider a secondary interface that transmits data at 300 MHz. Naturally, any external circuitry must also support clock speeds of up to 300 MHz. Now also consider that the secondary interface has a 50% blanking duration in its transmission interval. This means that the optimum frequency at which to transmit the secondary data is only 150 MHz. Thus, if the transmission speed at the secondary interface could be optimized, the external circuitry may only be required to support speeds up to 150 MHz.